This invention relates to devices for high speed CMOS integrated circuits, and specifically to commercial production of VLSI ICs having Si1xe2x88x92xGex layers by providing a layer of tensile strained silicon on a relaxed Si1xe2x88x92xGex layer to speed switching speeds for nMOS and pMOS transistors.
There are many publications describing a thick layer of Si1xe2x88x92xGex with graded Ge composition (x) followed by a thick, relaxed Si1xe2x88x92xGex layer of constant x capped by a thin silicon film under tensile strain, which is used for fabricating high drain drive current MOS transistors. Due to the lattice parameter mismatch between the Si1xe2x88x92xGex layers and the silicon substrate, there is a high density of misfit dislocations at the SiGe/Si substrate interface, accompanied by numerous threading dislocations in the SiGe, some of which propagate all the way to the surface. The total SiGe thickness is on the order of several microns and the density of threading dislocations at the surface is still on the order of 1xc3x97105 cmxe2x88x922. However, the very thick Si1xe2x88x92xGex layer and the high defect density of the conventional Si1xe2x88x92xGex process is not applicable for large-scale integrated circuit fabrication.
As demonstrated in S. Mantl et al., Strain relaxation of epitaxial SiGe layer on silicon (100) improved by hydrogen implantation, Nuclear Instruments and Methods in Physics Research B vol. 147, 29 (1999), and expanded upon in the above-identified related Applications 1 and 2, strain relaxed high quality Si1xe2x88x92xGex layers on silicon can be obtained by hydrogen ion implantation and annealing. Hydrogen ion implantation forms a narrow defect band slightly below the SiGe/Si interface. During subsequent annealing hydrogen platelets and cavities form, nucleating misfit dislocations, and giving rise to strong enhanced strain relaxation in the Si1xe2x88x92xGex epilayer. Hydrogen ions may also terminate some threading dislocations, preventing them from propagating toward the Si1xe2x88x92xGex surface. The related Applications 1 and 2 provide methods to reduce defect density and fabricate high drive current MOS transistors on a relaxed Si1xe2x88x92xGex film having thickness on the order of about only 300 nm. However, the defect density of the Si1xe2x88x92xGex film by these processes is still not suitable to very large-scale integrated circuit fabrication.
Related Application 3 discloses a method to further reduce the defect density in Si1xe2x88x92xGex films. In this related method, a buried amorphous region in the film is fabricated, e.g., with Si+ ion implantation, and then recrystallized through solid phase epitaxy (SPE) using as the seed the undamaged crystalline Si1xe2x88x92xGex region at the surface. However, the process window for making a buried amorphous region in SiGe may be rather narrow, because it has been consistently reported that SiGe is much more easily damaged by Si+ ion implantation than silicon, A. N. Larsen et al., MeV ion implantation induced damage in relaxed Si1xe2x88x92xGex, J. Appl. Phys., vol. 81, 2208 (1997); T. E. Haynes, et al., Damage accumulation during ion implantation of unstrained Si1xe2x88x92xGex alloy layers, Appl. Phys. Lett., vol. 61, 61 (1992); and D. Y. C. Lie, et al., Damage and strain in epitaxial GexSi1xe2x88x92x films irradiated with Si, J. Appl. Phys. Vol. 74, 6039 (1993). The critical dose for amorphization, (xcfx86c), decreases with increasing Ge concentration. This holds true for both strained and relaxed SiGe. For 2 MeV Si+ ions implanted at 27xc2x0 C., xcfx86c=6.7e14 cmxe2x88x922 for 20% Ge but only 4.6e14 cmxe2x88x922 for 30% Ge, per Larsen et al. For 100 keV Si+ ions implanted at room temperature, it has been reported that xcfx86c=7e14 cmxe2x88x922 and 2.5e14 cmxe2x88x922 for pure silicon and 10% Ge, respectively, Lie et al. For 80-90 keV Si+ ions implanted at 77K, it has been reported that xcfx86c=1.5, 1.0, 0.8, and 0.5 e14 cmxe2x88x922 for 0%, 15%, 50%, and 100% Ge, respectively, Haynes et al. This effect is thought to be due to both an increase in the average energy density per ion deposited in the collision cascade and a stabilization of the damage through a reduction of defect mobility, Haynes et al. and Lie et al. There is also a strong dependence on the wafer temperature during implant, T1, with the damage decreasing at higher T1, so xcfx86c will depend on temperature, Haynes et al.
A substrate having a Si1xe2x88x92xGex layer with graded composition is often used for growing tensile-strained silicon films, wherein the highest Ge concentration is located at the surface, as described in related Application 1. In this case, it may be even more difficult to avoid damaging or amorphizing the surface layer, because the higher Ge content makes the surface more susceptible to damage. If so, there will be no crystalline seed at the surface to nucleate SPE, and SPE will proceed only from the bottom, usually resulting in a heavily defected film. The instant invention is a method for preserving the crystallinity of the surface layer, in order to use it as a seed for SPE of the underlying amorphized Si1xe2x88x92xGex film.
A method of fabricating a Si1xe2x88x92XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1xe2x88x92XGeX layer on the silicon substrate forming a Si1xe2x88x92XGeX/Si interface there between; epitaxially growing a silicon cap on the Si1xe2x88x92XGeX layer; implanting hydrogen ions through the Si1xe2x88x92XGeX layer to a depth of between about 3 nm to 100 nm below the Si1xe2x88x92xGex/Si interface; amorphizing the Si1xe2x88x92XGeX layer to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650xc2x0 C. to 1100xc2x0 C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.
It is an object of the invention to provide a method to produce low defect density, 200 nm to 500 nm thick relaxed Si1xe2x88x92xGex films with Ge content of up to 50% or more at the top surface for large-scale integrated circuit application.
Another object of the invention is to provide a method of commercial production of VLSI ICs having Si1xe2x88x92xGex layers.
A further object of the invention is to provide a strained silicon layer on a relaxed Si1xe2x88x92xGex layer.
Another object of the invention is to provide Si/Si1xe2x88x92xGex structure which will speed up the switching speed of nMOS and pMOS transistors.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.